Current Issue : April - June Volume : 2021 Issue Number : 2 Articles : 5 Articles
Sensors based on capacitance detection are common in the field of inertial measurement and have the potential for miniaturization and low power consumption. In order to control and process such sensors, a novel digital-analog hybrid system-on-chip (SoC) is designed and implemented. The system includes a capacitor to voltage (C/V) conversion circuit and a band-pass sigma-delta modulator (BPSDM) as the analog-to-digital converter (ADC). The digital signal is processed by the dedicated circuit module based on the least mean square error demodulation (LMSD) algorithm on the chip. The low-power Cortex-M3 processor supports software implementation of control algorithms and circuit parameter configuration. The control signal is output through a digital BPSDM. The chip was taped out under SMIC 180 nm Complementary Metal Oxide Semiconductor (CMOS) technology and tested for performance. The result shows that the maximum operating frequency of the chip is 105 MHz. The total area is 77.43 mm2. When the system clock is set to 51.2 MHz, the static power consumption and dynamic power consumption of the digital system are 18 mW and 54 mW respectively....
The IEEE 802.1Qbv standard provides deterministic delay and low jitter guarantee for time-critical communication using a precomputed cyclic transmission schedule. Computing such transmission schedule requires routing the flows first, which significantly affects the quality of the schedule. So far off-the-shelf algorithms like load-balanced routing, which minimize the maximum scheduled traffic load (MSTL), have been used to accommodate more time-triggered traffic. However, they do not consider that the bandwidth utilization of periodic flows is decentralized and their criteria for bottleneck of scheduling are imprecise. In this paper, we firstly explore the combinability among different periods of flows, which can measure their ability to share bandwidth without conflict. Then, we propose a novel period-aware routing algorithm to reduce the scheduling bottleneck, thus more flows can be accommodated. The experiment results show that the success rate of scheduling is significantly improved compared to shortest path routing and load balanced routing....
The continuous market demands for high performance and energy-efficient computing systems have steered the computational paradigm and technologies towards nanoscale quantum-dot cellular automata (QCA). In this paper, novel energy- and areaefficient QCA-based adder/subtractor designs have been proposed. First, a QCA-based 3-input XOR gate is designed and then a full adder and a full subtractor are realized. The power consumption of the proposed design was tested via the QCAPro estimator tool with different kind of energy (c = 0.5 Ek, c = 1.0 Ek, and c = 1.5 Ek) at temperature T = 2 in Kelvin. QCADesigner 2.0.03 software was applied to evaluate the simulation results of the proposed designs. The proposed design has better complexity than the conventional designs in terms of cell count, area, and power dissipation....
In this paper, we propose a single chip fingerprint sensor with the algorithm processor and 16-bit MCU. The algorithm processor is a logic circuit that implements the GABOR filter and the THINNING step, which occupies 80% of the fingerprint image processing time. The rest of the algorithm is processed by embedded 16-bit MCU with small circuit volume, so all steps of the algorithm can be processed on the single chip without an external CPU. The capacitive sensing circuit was designed by applying the parasitic-insensitive integrator with the variable clock generator. The function was verified by Cadence Spectre for a 1-pixel sensor scheme and RTL and post simulation for digital blocks synthesized by Synopsys Design Compiler in 180n 2-poly 6-metal CMOS (complementary metal–oxide–semiconductor) process. The layout is done by automatic P&R for the full chip in a 96 × 96 pixel array. The chip area is 5010 μm × 5710 μm (28.61 mm2) and the gate count is 2,866,700. The result is compared with a conventional one. The proposed scheme can reduce the processing time by 57%....
This paper presents a low-complexity address generation unit (AGU) for multiuser detectors in interleave division multiple access (IDMA) systems. To this end, for the first time, all possible options for designing AGUs are first analyzed in detail. Subsequently, a complexity reduction technique is applied to each of those architectures. More specifically, some components in AGUs are relocated to make them shareable and removable without affecting the functionality. The complete transparency of such renovation makes it applicable to any existing multiuser detector without tailoring the interfacing components therein. Measuring the hardware complexity, all the resulting AGUs are compared with each other, and a new architecture simpler than the state-of-the-art one is developed. Implementation results in a 65 nm CMOS process, demonstrating that the proposed AGU can alleviate the equivalent gate count and the power consumption of the prior process by 13% and 31%, respectively....
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